The UVM Primer: A Step-by-Step Introduction to the Universal Verification Methodology

UVM can be pretty mysterious and complex, but Ray Salemi's book breaks it down into easily digested portions, with ample examples that work "out of the box" and let the student try different simulators and other tools. The only two changes I would make would be:1) Put the SystemVerilog, rather than the VHDL, models of the core design front-and-center, because many people lack either access to a mixed-language simulator or a desire to learn VHDL, which SystemVerilog is steadily rendering obsolete. Being in that first camp and not knowing about the provided SystemVerilog version of the tiny_ALU, I generated my own version -- not a big deal, but something to be aware of.2) I taught an advanced electrical engineering graduate course in VLSI design this past spring quarter, and I used this book heavily, as well as Chris Spear's "SystemVerilog For Verification." Students with a background in object oriented programming / C++ had a much easier time than their classmates, who struggled to learn OOP. The book should probably mention that SystemVerilog OOP is essential, so Spear's book might be a decent companion volume.Bottom line: great book -- affordable, to-the-point, builds steadliy chapter-by-chapter, and well-written (not surprising, since Salemi is also a novelist).

I love this book because it is clear to read and cuts out a lot of the superfluous details that make UVM hard to understand. If you are looking to learn UVM or freshen up for an interview. This is the place to start.

I enjoyed the tone of the book and the pacing. The content was also pitched at the level I was looking for (experienced VHDL developer, novice systemverilog, novice OOP, no knowledge UVM).The book is certainly only a primer and not much more but it enables the reader to understand web resources that seemed like totally foreign concepts only a day ago (about how long it takes to read and understand the book).4/5 as I think some of the code snippets are a little brief (there are complementary online resources but I’d rather have a little more inline) also it is expensive for what it is (but well priced compared to similar products).

I had been looking for a book that walked me from a testbench originally written in Verilog and how to evolve it to Systemverilog written in the Universal Verification Methodology (UVM) style. The writing in this primer is easily understood and entertaining. Support is available from the author's website in the form of downloadable SystemVerilog source code from his website. Additional support in the form of videos is also available on Youtube from his channel. To get the most from this book, you should be familiar with Java since SystemVerilog classes and methods are based heavily on Java.To fill in the necessary gaps, I would recommend "System Verilog for Verification" by Chris Spears as a follow up book.

Very helpful in understanding how UVM is different than a simple SV based testbench. It doesn't try to cover everything in UVM and instead focuses on just the basics - which is critical for getting a good foundation for further UVM training. The entire book & examples can be read in a weekend, making it valuable for quickly starting UVM work.

I had read other UVM books (such as Meade/Rosenberg) but the other books all assume you have some UVM foundation in place that you're building on top of. This is the only book I've found that shows a step-by-step approach to introducing UVM into an existing Verilog testbench. This approach lets me introduce things gradually, fully understanding each step of the way.Once you have a good UVM testbench up and running, this book is no longer very useful.

As such, you get an introduction to the concepts of UVM but you won’t get a deep understanding. The book is well written with lots of good code excerpts and highlighted code to focus your attention on the topic. It could have used a few more top level diagrams and a better explanation of the UVM library’s resources, which is why I am now searching for a book that goes into more depth. I guess that means the primer did its job!

Main UVM concepts like TLM, Analysis ports, driver sequencer connections are poorly examplained.First 10 chapters good. Sorry, but i felt like author made it more confusing that the UVM.